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Author
Rodríguez Vázquez, Ángel Benito (6)
Pérez Verdú, Belén (4)Medeiro Hidalgo, Fernando (3)Delgado Restituto, Manuel (2)Huertas Díaz, José Luis (2)Rosa Utrera, José Manuel de la (2)Espejo Meana, Servando Carlos (1)Rueda Rueda, Adoración (1)Río Fernández, Rocío del (1)Shoaei, Omid (1)... View MoreSubject
Switched-capacitor circuits (6)
ADSL (1)Analog-digital conversion (1)Analog-to-digital conversion (1)Analog-to-digital converters (1)Double sampling (1)IC oscillators (1)Nonlinear microelectronics (1)Oscillators (1)Sigma-delta (ΣΔ) modulators (1)... View MoreDate Issued2000 - 2006 (2)1990 - 1999 (3)1987 - 1989 (1)Funding agencyEuropean Union (UE) (2)Ministerio de Ciencia y Tecnología (MCYT). España (1)Has file(s)Yes (6)

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Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+ [Article]

Río Fernández, Rocío del; Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Delgado Restituto, Manuel; Medeiro Hidalgo, Fernando; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2004)
We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) ...
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Fourth-order cascade SC ΣΔ modulators: a comparative study [Article]

Medeiro Hidalgo, Fernando; Pérez Verdú, Belén; Rosa Utrera, José Manuel de la; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 1998)
Fourth-order cascade ΣΔ modulators are very well suited for IC implementation using analog sampled-data circuits because of their robust, stable operation and their capability to achieve high resolution and wide bandwidth ...
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A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology [Article]

Medeiro Hidalgo, Fernando; Pérez Verdú, Belén; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 1999)
This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, ...
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Chaos via a piecewise-linear switch ed-capacitor circuit [Article]

Rodríguez Vázquez, Ángel Benito; Rueda Rueda, Adoración; Pérez Verdú, Belén; Huertas Díaz, José Luis (Institution of Engineering and Technology, 1987)
A nonlinear switched-capacitor circuit that generates chaotic signals is reported. The circuit is described by a first-order piecewise-linear discrete equation that exhibits a chaotic dynamics. Experimental results ...
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A Chaotic Switched-Capacitor Circuit for 1/f Noise Generation [Article]

Delgado Restituto, Manuel; Rodríguez Vázquez, Ángel Benito; Espejo Meana, Servando Carlos; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1992)
A switched-capacitor circuit is reported for the generation of 1 / fYnoise. The circuit is described by a chaotic first-order piecewise-finear discrete map which yields a hopping transition between regions of chaotic motions ...
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Double-Sampling Single-Loop EA Modulator Topologies for Broad-band Applications [Article]

Yavari, Mohammad; Shoaei, Omid; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2006)
This paper presents novel double sampling high-order single loop sigma-delta modulator structures for wide-band applications. To alleviate the quantization noise folding into the inband frequency region, two previously ...
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