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A 2.5MHz 55dB Switched-Current BandPass ΣΔ Modulator for AM Signal Conversion [Presentation]
(Institute of Electrical and Electronics Engineers, 1997)
We present a Switched-Current (SI) fourth-order bandpass ΣΔ modulator IC prototype. It uses fully-differential circuits in 0.8μm CMOS technology to obtain a Dynamic Range (DR) larger than 55dB at 2.5MHz center frequency ...
High-order cascade multi-bit Σ∆ modulators for high-speed A/D conversion [Presentation]
(Universidad Carlos III, 1998)
The use of Sigma-Delta (Σ∆) modulation for analog-to-digital conversion (ADC) in the communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at ...
Global design of analog cells using statistical optimization techniques [Article]
(Springer, 1994)
We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU ...
Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology [Article]
(Wiley-Blackwell, 1997)
This paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an ...
Analysis of error mechanisms in switched-current Sigma-Delta modulators [Article]
(Springer, 2004)
This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, ...
Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors [Article]
(Institute of Electrical and Electronics Engineers, 1998)
This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of ...
Harmonic Distortion in Fully-Differential Switched-Current Sigma-Delta Modulators [Presentation]
(1999)
This paper presents a systematic analysis of the harmonic distortion in SD modulators (SDMs) implemented with fully-differential switched-current (SI) circuits. Closed form expressions are derived for the third-order ...
Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design [Presentation]
(1999)
This paper presents a detailed study on the transient response of SC integrators taking into account the effects of amplifier finite gain-bandwidth product and slew-rate during, unlike previous models, both the integration ...
Design Considerations for Multistandard Cascade ΣΔ Modulators [Presentation]
(2005)
This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design ...
Using CAD Tools for the Automatic Design of Low-Power ΣΔ Modulators [Presentation]
(1997)
This paper illustrates the use of a CAD methodology to design a high-resolution 2nd-order ZA modulator with optimized power con- sumption.The fabricated prototype in 0.7um CMOS technology features 16.4-bit resolution at ...