Artículo
Vulnerability Analysis of Trivium FPGA Implementations
Autor/es | Potestad Ordóñez, Francisco Eugenio
Jiménez Fernández, Carlos Jesús Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2017 |
Fecha de depósito | 2021-03-10 |
Publicado en |
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Resumen | Today, the large amount of information exchanged
among various devices as well as the growth of the
Internet of Things (IoT) demand the development of devices
that ensure secure communications, preventing malicious ... Today, the large amount of information exchanged among various devices as well as the growth of the Internet of Things (IoT) demand the development of devices that ensure secure communications, preventing malicious agents from tapping sensitive data. Indeed, information security is one of the key challenges to address within the IoT field. Due to the strong resource constraints in some IoT applications, cryptographic algorithms affording lightweight implementations have been proposed. They constitute the so-called lightweight cryptography. A prominent example is the Trivium stream cipher, one of the finalists of the eSTREAM project. Although cryptographic algorithms are certainly simpler, one of their most critical vulnerability sources in terms of hardware implementations is side channel attacks. In this paper, it is studied the vulnerability of field-programmable gate array (FPGA) implementations of Trivium stream ciphers against fault attacks. The design and implementation of a system that alters the clock signal and checks the outcome is also described. A comparison between real and simulated fault injections is carried out in order to examine their veracity. The vulnerability of different versions of the Trivium cipher and their routing dependences has been tested in two different FPGA families. The results show that all versions of the Trivium cipher are vulnerable to fault attacks, although some versions are more vulnerable than others. |
Agencias financiadoras | Ministerio de Economía y Competitividad (MINECO). España |
Identificador del proyecto | TEC2013-45523-R
TEC2016-80549-R CSIC 201550E039 |
Cita | Potestad Ordóñez, F.E., Jiménez Fernández, C.J. y Valencia Barrero, M. (2017). Vulnerability Analysis of Trivium FPGA Implementations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 (12), 3380-3389. |
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