dc.creator | Pérez Carrasco, José Antonio | es |
dc.creator | Zamarreño Ramos, Carlos | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2020-10-22T10:46:31Z | |
dc.date.available | 2020-10-22T10:46:31Z | |
dc.date.issued | 2010 | |
dc.identifier.citation | Pérez Carrasco, J.A., Zamarreño Ramos, C., Serrano Gotarredona, M.T. y Linares Barranco, B. (2010). On neuromorphic spiking architectures for asynchronous STDP memristive systems. En ISCAS 2010: IEEE International Symposium on Circuits and Systems (1659-1662), Paris, France: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-4244-5308-5 | es |
dc.identifier.issn | 0271-4302 | es |
dc.identifier.uri | https://hdl.handle.net/11441/102149 | |
dc.description.abstract | Neuromorphic circuits and systems techniques have great potential for exploiting novel nanotechnology devices, which suffer from great parametric spread and high defect rate. In this paper we explore some potential ways of building neural network systems for sophisticated pattern recognition tasks using memristors. We will focus on spiking signal coding because of its energy and information coding efficiency, and concentrate on Convolutional Neural Networks because of their good scaling behavior, both in terms of number of synapses and temporal processing delay. We propose asynchronous architectures that exploit memristive synapses with specially designed neurons that allow for arbitrary scalability as well as STDP learning. We present some behavioral simulation results for small neural arrays using electrical circuit simulators, and system level spike processing results on human detection using a custom made event based simulator. | es |
dc.description.sponsorship | European Union 216777 (NABAB) | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TEC2006-11730-C03-01 | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2009-10639-C04-01 | es |
dc.description.sponsorship | Junta de Andalucía P06-TIC-01417 | es |
dc.format | application/pdf | es |
dc.format.extent | 4 | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | ISCAS 2010: IEEE International Symposium on Circuits and Systems (2010), p 1659-1662 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | On neuromorphic spiking architectures for asynchronous STDP memristive systems | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Teoría de la Señal y Comunicaciones | es |
dc.relation.projectID | 216777 (NABAB) | es |
dc.relation.projectID | TEC2006-11730-C03-01 | es |
dc.relation.projectID | TEC2009-10639-C04-01 | es |
dc.relation.projectID | P06-TIC-01417 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/5537484 | es |
dc.identifier.doi | 10.1109/ISCAS.2010.5537484 | es |
dc.publication.initialPage | 1659 | es |
dc.publication.endPage | 1662 | es |
dc.eventtitle | ISCAS 2010: IEEE International Symposium on Circuits and Systems | es |
dc.eventinstitution | Paris, France | es |
dc.relation.publicationplace | New York, USA | es |
dc.contributor.funder | European Union (UE) | es |
dc.contributor.funder | Ministerio de Educación y Ciencia (MEC). España | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |
dc.contributor.funder | Junta de Andalucía | es |