Mostrar el registro sencillo del ítem

Ponencia

dc.creatorPérez Carrasco, José Antonioes
dc.creatorZamarreño Ramos, Carloses
dc.creatorSerrano Gotarredona, María Teresaes
dc.creatorLinares Barranco, Bernabées
dc.date.accessioned2020-10-22T10:46:31Z
dc.date.available2020-10-22T10:46:31Z
dc.date.issued2010
dc.identifier.citationPérez Carrasco, J.A., Zamarreño Ramos, C., Serrano Gotarredona, M.T. y Linares Barranco, B. (2010). On neuromorphic spiking architectures for asynchronous STDP memristive systems. En ISCAS 2010: IEEE International Symposium on Circuits and Systems (1659-1662), Paris, France: IEEE Computer Society.
dc.identifier.isbn978-1-4244-5308-5es
dc.identifier.issn0271-4302es
dc.identifier.urihttps://hdl.handle.net/11441/102149
dc.description.abstractNeuromorphic circuits and systems techniques have great potential for exploiting novel nanotechnology devices, which suffer from great parametric spread and high defect rate. In this paper we explore some potential ways of building neural network systems for sophisticated pattern recognition tasks using memristors. We will focus on spiking signal coding because of its energy and information coding efficiency, and concentrate on Convolutional Neural Networks because of their good scaling behavior, both in terms of number of synapses and temporal processing delay. We propose asynchronous architectures that exploit memristive synapses with specially designed neurons that allow for arbitrary scalability as well as STDP learning. We present some behavioral simulation results for small neural arrays using electrical circuit simulators, and system level spike processing results on human detection using a custom made event based simulator.es
dc.description.sponsorshipEuropean Union 216777 (NABAB)es
dc.description.sponsorshipMinisterio de Educación y Ciencia TEC2006-11730-C03-01es
dc.description.sponsorshipMinisterio de Economía y Competitividad TEC2009-10639-C04-01es
dc.description.sponsorshipJunta de Andalucía P06-TIC-01417es
dc.formatapplication/pdfes
dc.format.extent4es
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofISCAS 2010: IEEE International Symposium on Circuits and Systems (2010), p 1659-1662
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleOn neuromorphic spiking architectures for asynchronous STDP memristive systemses
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Teoría de la Señal y Comunicacioneses
dc.relation.projectID216777 (NABAB)es
dc.relation.projectIDTEC2006-11730-C03-01es
dc.relation.projectIDTEC2009-10639-C04-01es
dc.relation.projectIDP06-TIC-01417es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/5537484es
dc.identifier.doi10.1109/ISCAS.2010.5537484es
dc.publication.initialPage1659es
dc.publication.endPage1662es
dc.eventtitleISCAS 2010: IEEE International Symposium on Circuits and Systemses
dc.eventinstitutionParis, Francees
dc.relation.publicationplaceNew York, USAes
dc.contributor.funderEuropean Union (UE)es
dc.contributor.funderMinisterio de Educación y Ciencia (MEC). Españaes
dc.contributor.funderMinisterio de Economía y Competitividad (MINECO). Españaes
dc.contributor.funderJunta de Andalucíaes

FicherosTamañoFormatoVerDescripción
On neuromorphic spiking archit ...837.6KbIcon   [PDF] Ver/Abrir  

Este registro aparece en las siguientes colecciones

Mostrar el registro sencillo del ítem

Attribution-NonCommercial-NoDerivatives 4.0 Internacional
Excepto si se señala otra cosa, la licencia del ítem se describe como: Attribution-NonCommercial-NoDerivatives 4.0 Internacional