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dc.creatorPérez Carrasco, José Antonioes
dc.creatorSerrano Gotarredona, María Teresaes
dc.creatorSerrano Gotarredona, Claraes
dc.creatorAcha Piñero, Begoñaes
dc.creatorLinares Barranco, Bernabées
dc.date.accessioned2020-10-22T07:35:56Z
dc.date.available2020-10-22T07:35:56Z
dc.date.issued2008
dc.identifier.citationPérez Carrasco, J.A., Serrano Gotarredona, M.T., Serrano Gotarredona, C., Acha Piñero, B. y Linares Barranco, B. (2008). High-Speed Character Recognition System based on a complex hierarchical AER architecture. En ISCAS 2008: IEEE International Symposium on Circuits and Systems (2150-2153), Seattle, USA: IEEE Computer Society.
dc.identifier.isbn978-1-4244-1683-7es
dc.identifier.issn0271-4302es
dc.identifier.urihttps://hdl.handle.net/11441/102134
dc.description.abstractIn this paper we briefly summarize the fundamental properties of spikes processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does not rely on sensing and processing sequences of frames, and because it allows for complex hierarchically structured cortical-like layers for sophisticated processing. The paper describes briefly cortex-like spiking vision processing principles, and the AER (Address Event Representation) technique used in hardware spiking systems. Afterwards an example application is described, which is a simplification of Fukushima’s Neocognitron. Realistic behavioral simulations based on existing AER hardware characteristics, reveal that the simplified neocognitron, although it processes 52 large kernel convolutions, is capable of performing recognition in less than 10µs.es
dc.description.sponsorshipMinisterio de Educación y Ciencia TIC-2003-08164-C03-01es
dc.description.sponsorshipMinisterio de Educación y Ciencia TEC-2006-11730-C03-01es
dc.description.sponsorshipEuropean Union IST-2001-34124 (CAVIAR)es
dc.description.sponsorshipJunta de Andalucía P06-TIC-01417es
dc.formatapplication/pdfes
dc.format.extent4es
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofISCAS 2008: IEEE International Symposium on Circuits and Systems (2008), p 2150-2153
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleHigh-Speed Character Recognition System based on a complex hierarchical AER architecturees
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Teoría de la Señal y Comunicacioneses
dc.relation.projectIDTIC-2003-08164-C03-01es
dc.relation.projectIDTEC-2006-11730-C03-01es
dc.relation.projectIDIST-2001-34124 (CAVIAR)es
dc.relation.projectIDP06-TIC-01417es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/4541876es
dc.identifier.doi10.1109/ISCAS.2008.4541876es
dc.publication.initialPage2150es
dc.publication.endPage2153es
dc.eventtitleISCAS 2008: IEEE International Symposium on Circuits and Systemses
dc.eventinstitutionSeattle, USAes
dc.relation.publicationplaceNew York, USAes
dc.contributor.funderMinisterio de Educación y Ciencia (MEC). Españaes
dc.contributor.funderMinisterio de Educación y Ciencia (MEC). Españaes
dc.contributor.funderEuropean Union (UE)es
dc.contributor.funderJunta de Andalucíaes

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