dc.creator | Pérez Carrasco, José Antonio | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Serrano Gotarredona, Clara | es |
dc.creator | Acha Piñero, Begoña | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2020-10-22T07:35:56Z | |
dc.date.available | 2020-10-22T07:35:56Z | |
dc.date.issued | 2008 | |
dc.identifier.citation | Pérez Carrasco, J.A., Serrano Gotarredona, M.T., Serrano Gotarredona, C., Acha Piñero, B. y Linares Barranco, B. (2008). High-Speed Character Recognition System based on a complex hierarchical AER architecture. En ISCAS 2008: IEEE International Symposium on Circuits and Systems (2150-2153), Seattle, USA: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-4244-1683-7 | es |
dc.identifier.issn | 0271-4302 | es |
dc.identifier.uri | https://hdl.handle.net/11441/102134 | |
dc.description.abstract | In this paper we briefly summarize the fundamental
properties of spikes processing applied to artificial vision
systems. This sensing and processing technology is capable of
very high speed throughput, because it does not rely on
sensing and processing sequences of frames, and because it
allows for complex hierarchically structured cortical-like
layers for sophisticated processing. The paper describes
briefly cortex-like spiking vision processing principles, and
the AER (Address Event Representation) technique used in
hardware spiking systems. Afterwards an example
application is described, which is a simplification of
Fukushima’s Neocognitron. Realistic behavioral simulations
based on existing AER hardware characteristics, reveal that
the simplified neocognitron, although it processes 52 large
kernel convolutions, is capable of performing recognition in
less than 10µs. | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TIC-2003-08164-C03-01 | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TEC-2006-11730-C03-01 | es |
dc.description.sponsorship | European Union IST-2001-34124 (CAVIAR) | es |
dc.description.sponsorship | Junta de Andalucía P06-TIC-01417 | es |
dc.format | application/pdf | es |
dc.format.extent | 4 | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | ISCAS 2008: IEEE International Symposium on Circuits and Systems (2008), p 2150-2153 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | High-Speed Character Recognition System based on a complex hierarchical AER architecture | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Teoría de la Señal y Comunicaciones | es |
dc.relation.projectID | TIC-2003-08164-C03-01 | es |
dc.relation.projectID | TEC-2006-11730-C03-01 | es |
dc.relation.projectID | IST-2001-34124 (CAVIAR) | es |
dc.relation.projectID | P06-TIC-01417 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/4541876 | es |
dc.identifier.doi | 10.1109/ISCAS.2008.4541876 | es |
dc.publication.initialPage | 2150 | es |
dc.publication.endPage | 2153 | es |
dc.eventtitle | ISCAS 2008: IEEE International Symposium on Circuits and Systems | es |
dc.eventinstitution | Seattle, USA | es |
dc.relation.publicationplace | New York, USA | es |
dc.contributor.funder | Ministerio de Educación y Ciencia (MEC). España | es |
dc.contributor.funder | Ministerio de Educación y Ciencia (MEC). España | es |
dc.contributor.funder | European Union (UE) | es |
dc.contributor.funder | Junta de Andalucía | es |