Now showing items 1-20 of 26

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      A Proposal for a New Way of Classifying Network Security Metrics: Study of the Information Collected through a Honeypot  [Presentation]

      Carrasco Muñoz, Alejandro; Ropero Rodríguez, Jorge; Ruiz de Clavijo Vázquez, Paulino; Benjumea Mondéjar, Jaime; Luque Sendra, Amalia (IEEE Computer Society, 2018)
      Nowadays, honeypots are a key tool to attract attackers and study their activity. They help us in the tasks of evaluating attacker's behaviour, discovering new types of attacks, and collecting information and statistics ...
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      Application of Internode model to global power consumption estimation in SCMOS gates  [Article]

      Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)
      In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its ...
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      Aprendizaje interdisciplinar de la electrónica y las comunicaciones  [Article]

      Yúfera García, Alberto; Fortet Roura, Pedro; Ruiz de Clavijo Vázquez, Paulino; Chico, J.J.; Bellido Díaz, Manuel Jesús (Universidad de Sevilla: Instituto de Ciencias de la Educación, 2003)
      En este proyecto de innovación docente se pretende profundizar en el conocimiento de la base teórica, la construcción de los modelos matemáticos físicos que son la base de los diseños electrónicos, mediante el montaje, ...
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      Automated performance evaluation of skew-tolerant clocking schemes  [Article]

      Guerrero Martos, David; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Millán Calderón, Alejandro; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Taylor and Francis Online, 2006)
      In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: ...
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      Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)  [Article]

      Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David (Springer, 2002-08-27)
      In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model ...
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      Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits  [Chapter of Book]

      Guerrero Martos, David; Wilke, G.; Güntzel, J.L.; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Millán Calderón, Alejandro (Springer, 2003)
      The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on each combinational block of the circuit. A key factor in timing analysis is the election ...
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      Degradation Delay Model Extension to CMOS Gates  [Chapter of Book]

      Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (Springer, 2000)
      This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are ...
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      Desarrollo de una aplicación en internet para la autoevaluación de alumnos del área de Producción animal  [Presentation]

      Fernández Cabanás, Víctor Manuel; Caravaca Rodríguez, Francisco Pascual; Castel Genís, José María; Delgado Pertíñez, Manuel; Alcalde Aldea, María Jesús; González Redondo, Pedro; Mena Guerrero, Yolanda; Barros Pérez, José; Ruiz de Clavijo Vázquez, Paulino; Millán Calderón, Alejandro (Universidad de Sevilla. Instituto de Ciencias de la Educación, 2003)
      En este proyecto se ha tratado de desarrollar una herramienta informática que permita a los alumnos de la asignatura Zootecnia General de la EUITA comprobar sus conocimientos sobre esta materia y, al mismo tiempo, ...
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      Design of a FFT/IFFT module as an IP core suitable for embedded systems  [Presentation]

      Viejo Cortés, Julián; Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Muñoz Blanco, Antonio (IEEE Computer Society, 2007)
      In this work, we have laid the foundations that allow us to accomplish the implementation of a FFT/IFFT module as an IP core. The main objective is to design a configurable optimized core that can be integrated as a ...
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      Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level  [Chapter of Book]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David (Springer, 2002)
      This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic ...
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      Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements  [Presentation]

      Viejo Cortés, Julián; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Ostúa Arangüena, Enrique; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David (IEEE Computer Society, 2006)
      This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network ...
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      Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation  [Article]

      Viejo Cortés, Julián; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Ruiz de Clavijo Vázquez, Paulino (IEEE Computer Society, 2011)
      Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in ...
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      Gate-Level Simulation of CMOS Circuits Using the IDDM Model  [Presentation]

      Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2001)
      Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is ...
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      HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model  [Presentation]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2001)
      This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm ...
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      Inertial and Degradation Delay Model for CMOS Logic Gates  [Presentation]

      Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2000)
      The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial ...
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      Internode: Internal Node Logic Computational Model  [Presentation]

      Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Guerrero Martos, David; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique (IEEE Computer Society, 2003)
      In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal ...
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      Logic-Level Fast Current Simulation for Digital CMOS Circuits  [Chapter of Book]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)
      Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of ...
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      Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level  [Chapter of Book]

      Baena Oliva, María del Carmen; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Jiménez Fernández, Carlos Jesús; Valencia Barrero, Manuel (Springer, 2002)
      Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) ...
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      Metodología PBL en modo colaborativo aplicada al diseño de un SoC  [Presentation]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Viejo Cortés, Julián; Bellido Díaz, Manuel Jesús; Ostúa Arangüena, Enrique (Universidad de Sevilla, 2016)
      Dado el carácter principalmente práctico en las asignaturas de los másteres universitarios la metodología PBL es ampliamente utilizada. Este trabajo presenta una experiencia docente de varios años, donde se aplica PBL, ...
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      Minimalistic SDHC-SPI hardware reader module for boot loader applications  [Article]

      Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Viejo Cortés, Julián; Guerrero Martos, David (Elsevier, 2017)
      This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having ...