Now showing items 1-14 of 14

    • Icon

      Application of Internode model to global power consumption estimation in SCMOS gates  [Article]

      Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)
      In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its ...
    • Icon

      Automated performance evaluation of skew-tolerant clocking schemes  [Article]

      Guerrero Martos, David; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Millán Calderón, Alejandro; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Taylor and Francis Online, 2006)
      In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: ...
    • Icon

      Building a basic membrane computer  [Presentation]

      Millán Calderón, Alejandro; Viejo Cortés, Julián; Quirós Carmona, Juan; Bellido Díaz, Manuel Jesús; Guerrero Martos, David; Ostúa Arangüena, Enrique (Fénix, 2016)
      In this work, we present the building of two well-known membrane com- puters (squares generator and divisor test). Although they are very basic machines they present problems common to every P system (competition, parallel ...
    • Icon

      Design and implementation of a suitable core for on-chip long-term verification  [Presentation]

      Viejo Cortés, Julián; Villar de Ossorno, José Ignacio; Juan Chico, Jorge; Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Ostúa Arangüena, Enrique (IEEE Computer Society, 2010)
      Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the long-term verification of industrial embedded systems, forcing the designer to implement ad-hoc verification solutions. ...
    • Icon

      Design of a FFT/IFFT module as an IP core suitable for embedded systems  [Presentation]

      Viejo Cortés, Julián; Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Muñoz Blanco, Antonio (IEEE Computer Society, 2007)
      In this work, we have laid the foundations that allow us to accomplish the implementation of a FFT/IFFT module as an IP core. The main objective is to design a configurable optimized core that can be integrated as a ...
    • Icon

      Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements  [Presentation]

      Viejo Cortés, Julián; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Ostúa Arangüena, Enrique; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David (IEEE Computer Society, 2006)
      This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network ...
    • Icon

      Internode: Internal Node Logic Computational Model  [Presentation]

      Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Guerrero Martos, David; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique (IEEE Computer Society, 2003)
      In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal ...
    • Icon

      Logic-Level Fast Current Simulation for Digital CMOS Circuits  [Chapter of Book]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)
      Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of ...
    • Icon

      Long-term on-chip verification of systems with logical events scattered in time  [Article]

      Viejo Cortés, Julián; Villar de Ossorno, José Ignacio; Juan Chico, Jorge; Millán Calderón, Alejandro; Ostúa Arangüena, Enrique; Quirós Carmona, Juan (Elsevier, 2012)
      Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the longterm verification of industrial embedded systems, forcing the designer to implement ad hoc verification solutions. ...
    • Icon

      Metodología PBL en modo colaborativo aplicada al diseño de un SoC  [Presentation]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Viejo Cortés, Julián; Bellido Díaz, Manuel Jesús; Ostúa Arangüena, Enrique (Universidad de Sevilla, 2016)
      Dado el carácter principalmente práctico en las asignaturas de los másteres universitarios la metodología PBL es ampliamente utilizada. Este trabajo presenta una experiencia docente de varios años, donde se aplica PBL, ...
    • Icon

      Minimalistic SDHC-SPI hardware reader module for boot loader applications  [Article]

      Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Viejo Cortés, Julián; Guerrero Martos, David (Elsevier, 2017)
      This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having ...
    • Icon

      NanoFS: a hardware-oriented file system  [Article]

      Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Viejo Cortés, Julián; Guerrero Martos, David (IEEE Computer Society, 2013)
      NanoFS is a novel file system for embedded systems and storage-class memories (like flash) and is specially designed to be directly implemented in hardware. NanoFS is based on an original internal layout intended to achieve ...
    • Icon

      Signal Sampling Based Transition Modeling for Digital Gates Characterization  [Article]

      Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique (Springer, 2004)
      Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. ...
    • Icon

      Static Power Consumption in CMOS Gates Using Independent Bodies  [Chapter of Book]

      Guerrero Martos, David; Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2007)
      It has been reported that the use of independent body terminals for series transistors in static bulk-CMOS gates improves their timing and dynamic power characteristics. In this paper, the static power consumption of ...