Browsing by Author "Núñez Martínez, Juan"
Now showing items 1-20 of 34
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Presentation
Assessing application areas for tunnel transistor technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2016)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Presentation
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
(Instituto Nacional de Astrofísica, Óptica y Electrónica; Universidad de Sevilla, 2012-03)The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic ...
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Article
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
(Institute of Electrical and Electronics Engineers, 2016)In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ...
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Article
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
(Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Presentation
Complementary tunnel gate topology to reduce crosstalk effects
(Institute of Electrical and Electronics Engineers (IEEE), 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome ...
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PhD Thesis
Desarrollo y evaluación de arquitecturas lógicas basadas en Nanopipeline.
(2018-07-17)El potencial de la lógica dinámica, con sus fases de precarga y evaluación es una solución muy estudiada y aplicada, para ...
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Article
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
(Springer, 2016)This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low ...
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Article
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications
(Frontiers Media, 2021)Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called “data ...
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PhD Thesis
Diseño lógico de circuitos digitales usando dispositivos con característica NDR
(2011-02-04)En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos ...
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Presentation
DOE based high-performance gate-level pipelines
(Institute of Electrical and Electronics Engineers, 2014)Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in ...
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Article
Domino inspired MOBILE networks
(Institute of Electrical and Electronics Engineers, 2012)MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
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Presentation
Efficient realization of RTD-CMOS logic gates
(2011)The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit ...
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Article
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
(Institute of Electrical and Electronics Engineers, 2014)Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable ...
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Presentation
Exploring logic architectures suitable for TFETs devices
(Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates ...
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Article
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs
(IEEE, 2021)The design of secure circuits in emerging technologies is an appealing area that requires new efforts and attention as an ...
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Presentation
Holding Dissapearance in RTD-based Quantizers
(Laboratoire TIMA, 2007)Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition ...
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Article
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase
(IEEE, 2022)Brain-inspired computing employs devices and architectures that emulate biological functions for more adaptive and ...
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Article
Hybrid-Phase-Transition FET Devices for Logic Computation
(IEEE, 2020)Hybrid-phase-transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of ...
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Article
Impact of the RT-level architecture on the power performance of tunnel transistor circuits
(Wiley, 2018)Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being ...
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Presentation
Improving robustness of dynamic logic based pipelines
(Institute of Electrical and Electronics Engineers, 2016)Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in ...