Now showing items 1-20 of 26

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      Aplicaciones docentes del diseño de un pico-procesador  [Presentation]

      Jiménez Fernández, Carlos Jesús; Baena Oliva, María del Carmen; Parra Fernández, María del Pilar; Valencia Barrero, Manuel (Universidad de Sevilla, 2016)
      El conocimiento de la estructura interna y del mecanismo de funcionamiento de microprocesadores es una parte muy importante en la formación de ingenieros en electrónica e informática. Este conocimiento puede profundizarse ...
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      Application of Internode model to global power consumption estimation in SCMOS gates  [Article]

      Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)
      In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its ...
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      Automated performance evaluation of skew-tolerant clocking schemes  [Article]

      Guerrero Martos, David; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Millán Calderón, Alejandro; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Taylor and Francis Online, 2006)
      In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: ...
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      Building a basic membrane computer  [Presentation]

      Millán Calderón, Alejandro; Viejo Cortés, Julián; Quirós Carmona, Juan; Bellido Díaz, Manuel Jesús; Guerrero Martos, David; Ostúa Arangüena, Enrique (Fénix, 2016)
      In this work, we present the building of two well-known membrane com- puters (squares generator and divisor test). Although they are very basic machines they present problems common to every P system (competition, parallel ...
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      Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)  [Article]

      Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David (Springer, 2002-08-27)
      In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model ...
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      Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits  [Chapter of Book]

      Guerrero Martos, David; Wilke, G.; Güntzel, J.L.; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Millán Calderón, Alejandro (Springer, 2003)
      The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on each combinational block of the circuit. A key factor in timing analysis is the election ...
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      Creación de carteles autoexplicativos para laboratorios de electrónica  [Presentation]

      Jiménez Fernández, Carlos Jesús; Parra Fernández, María del Pilar; Baena Oliva, María del Carmen; Valencia Barrero, Manuel (Universidad de Sevilla, 2016)
      Se presenta un proyecto cuyo objetivo ha sido ha sido la creación de carteles que, a modo de tutoriales resumidos, muestran de forma muy visual las tareas básicas a realizar en los laboratorios de electrónica. Están ...
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      Desarrollo de una aplicación en internet para la autoevaluación de alumnos del área de Producción animal  [Presentation]

      Fernández Cabanás, Víctor Manuel; Caravaca Rodríguez, Francisco Pascual; Castel Genís, José María; Delgado Pertíñez, Manuel; Alcalde Aldea, María Jesús; González Redondo, Pedro; Mena Guerrero, Yolanda; Barros Pérez, José; Ruiz de Clavijo Vázquez, Paulino; Millán Calderón, Alejandro (Universidad de Sevilla. Instituto de Ciencias de la Educación, 2003)
      En este proyecto se ha tratado de desarrollar una herramienta informática que permita a los alumnos de la asignatura Zootecnia General de la EUITA comprobar sus conocimientos sobre esta materia y, al mismo tiempo, ...
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      Design and implementation of a suitable core for on-chip long-term verification  [Presentation]

      Viejo Cortés, Julián; Villar de Ossorno, José Ignacio; Juan Chico, Jorge; Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Ostúa Arangüena, Enrique (IEEE Computer Society, 2010)
      Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the long-term verification of industrial embedded systems, forcing the designer to implement ad-hoc verification solutions. ...
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      Design of a FFT/IFFT module as an IP core suitable for embedded systems  [Presentation]

      Viejo Cortés, Julián; Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Muñoz Blanco, Antonio (IEEE Computer Society, 2007)
      In this work, we have laid the foundations that allow us to accomplish the implementation of a FFT/IFFT module as an IP core. The main objective is to design a configurable optimized core that can be integrated as a ...
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      Diseño e Implementación sobre FPGA de Sistemas Digitales de bajo coste para la Sincronización de Equipos sobre Redes de Comunicación usando el protocolo SNTP  [PhD Thesis]

      Viejo Cortés, Julián (2011)
      En este documento se presenta el trabajo de tesis doctoral realizado dentro del Programa de Doctorado "Informática Industrial" del Departamento de Tecnología Electrónica de la Universidad de Sevilla. Dicho trabajo consiste ...
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      Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level  [Chapter of Book]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David (Springer, 2002)
      This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic ...
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      Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements  [Presentation]

      Viejo Cortés, Julián; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Ostúa Arangüena, Enrique; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David (IEEE Computer Society, 2006)
      This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network ...
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      Fast Hardware Implementations of Static P Systems  [Article]

      Quirós Carmona, Juan; Verlan, Sergey; Viejo Cortés, Julián; Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús (2016)
      In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each ...
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      Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation  [Article]

      Viejo Cortés, Julián; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Ruiz de Clavijo Vázquez, Paulino (IEEE Computer Society, 2011)
      Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in ...
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      Implementación sobre hardware reconfigurable de una arquitectura no determinista, paralela y distribuida de alto rendimiento, basada en modelos de computación con membranas  [PhD Thesis]

      Quirós Carmona, Juan (2016-01-26)
      En este documento se presenta el trabajo de tesis doctoral realizado dentro del Programa de Doctorado “Informática Industrial” del Departamento de Tecnología Electrónica de la Universidad de Sevilla. Recoge la investigación ...
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      Internode: Internal Node Logic Computational Model  [Presentation]

      Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Guerrero Martos, David; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique (IEEE Computer Society, 2003)
      In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal ...
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      Logic-Level Fast Current Simulation for Digital CMOS Circuits  [Chapter of Book]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)
      Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of ...
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      Long-term on-chip verification of systems with logical events scattered in time  [Article]

      Viejo Cortés, Julián; Villar de Ossorno, José Ignacio; Juan Chico, Jorge; Millán Calderón, Alejandro; Ostúa Arangüena, Enrique; Quirós Carmona, Juan (Elsevier, 2012)
      Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the longterm verification of industrial embedded systems, forcing the designer to implement ad hoc verification solutions. ...
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      Metodología de evaluación continua para grupos numerosos en Procesamiento de Señales Multimedia  [Presentation]

      Molina Cantero, Alberto Jesús; Mora Merchán, Javier María; Cabrera Cabrera, Rafael; Rivera-Romero, Octavio; Gómez González, Isabel María; Merino Monge, Manuel (Universidad de Sevilla, 2016)
      La asignatura de Procesamiento de Señales Multimedia utiliza una metodología de evaluación continua consistente en la realización de siete proyectos basados en Octave con periodicidad bisemanal y de tests de evaluación ...