Now showing items 1-20 of 114

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      10mhz cmos ota-c voltage-controlled quadrature oscillator  [Article]

      Linares Barranco, Bernabé; Rodríguez Vázquez, Ángel Benito; Sánchez Sinencio, Edgar; Huertas Díaz, José Luis (Institution of Engineering and Technology, 1989)
      A quadrature-type voltage-controlled oscillator with operational transconductance amplifiers and capacitors (OTA-C) is presented. A monolithic integrated CMOS test circuit is introduced to verify theoretical results. The ...
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      7-decade tuning range CMOS OTA-C sinusoidal VCO  [Article]

      Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 1998)
      A new operational transconductance amplifier-capacitor (OTA-C) based sinusoidal voltage-controlled oscillator (VCO) has been designed and fabricated, the oscillation frequency of which can be tuned from 74 mHz to 1 MHz. ...
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      A 3.6 μ s latency asynchronous frame-free event-driven dynamic-vision-sensor  [Article]

      Leñero Bardallo, Juan Antonio; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2011)
      This paper presents a 128 × 128 dynamic vision sensor. Each pixel detects temporal changes in the local illumination. A minimum illumination temporal contrast of 10% can be detected. A compact preamplification stage has ...
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      A 32, x, 32 pixel convolution processor chip for address event vision sensors with 155 ns event latency and 20 meps throughput  [Article]

      Camuñas Mesa, Luis Alejandro; Acosta Jiménez, Antonio José; Zamarreño Ramos, Carlos; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2010)
      This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional frame-constraint vision systems, in event-driven vision there is no need for frames. In frame-free ...
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      A basic building block approach to CMOS design of analog neuro/fuzzy systems  [Presentation]

      Vidal Verdú, Fernando; Rodríguez Vázquez, Ángel Benito; Linares Barranco, Bernabé; Sánchez Sinencio, Edgar (Institute of Electrical and Electronics Engineers, 1994)
      Outlines a systematic approach to design fuzzy inference systems using analog integrated circuits in standard CMOS VLSI technologies. The proposed circuit building blocks are arranged in a layered neuro/fuzzy architecture ...
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      A bioinspired 128x128 pixel dynamic-vision-sensor  [Presentation]

      Serrano Gotarredona, María Teresa; Leñero Bardallo, Juan Antonio; Linares Barranco, Bernabé (2011)
      This paper presents a 128x128 dynamic vision sensor. Each pixel detects temporal changes in the local illumination. A minimum illumination temporal contrast of 10% can be detected. A compact preamplification stage has ...
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      A calibration technique for very low current and compact tunable neuromorphic cells: Application to 5-bit 20nA DACs  [Article]

      Leñero Bardallo, Juan Antonio; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2008)
      Low current applications, like neuromorphic circuits, where operating currents can be as low as a few nanoamperes or less, suffer from huge transistor mismatches, resulting in around or less than 1-bit precisions. Recently, ...
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      A CMOS analog adaptive BAM with on-chip learning and weight refreshing  [Article]

      Linares Barranco, Bernabé; Sánchez Sinencio, Edgar; Rodríguez Vázquez, Ángel Benito; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1993)
      In this paper we will extend the transconductance-mode (T-mode) approach [1] to implement analog continuous-time neural network hardware systems to include on-chip Hebbian learning and on-chip analog weight storage capability. ...
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      A CMOS Implementation of Fitzhugh-Nagumo Neuron Model  [Presentation]

      Linares Barranco, Bernabé; Sánchez Sinencio, Edgar; Rodríguez Vázquez, Ángel Benito; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1990)
      A CMOS circuit is proposed that emulates FitzHugh-Nagumo's differential equations using OTAs, diode connected MOSFETs and capacitors. These equations model the fundamental behavior of biological neuron cells. Fitz- ...
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      A Configurable Event-Driven Convolutional Node with Rate Saturation Mechanism for Modular ConvNet Systems Implementation  [Article]

      Camuñas Mesa, Luis Alejandro; Domínguez Cordero, Yaisel L.; Linares Barranco, Alejandro; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Frontiers Media, 2018)
      Convolutional Neural Networks (ConvNets) are a particular type of neural network often used for many applications like image recognition, video analysis or natural language processing. They are inspired by the human brain, ...
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      A five-decade dynamic-range ambient-light-independent calibrated signed-spatial-contrast AER retina with 0.1-ms latency and optional time-to-first-spike mode  [Article]

      Leñero Bardallo, Juan Antonio; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2010)
      Address Event Representation (AER) is an emergent technology for assembling modular multiblock bio-inspired sensory and processing systems. Visual sensors (retinae) are among the first AER modules to be reported since the ...
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      A general translinear principle for subthreshold MOS transistors  [Article]

      Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé; Andreou, Andreas G. (Institute of Electrical and Electronics Engineers, 1999)
      This paper revises the conditions under which the translinear principle can be fully exploited for MOS transistors operating in subthreshold. Due to the exponential nature of subthreshold MOS transistors, the translinear ...
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      A high-precision current-mode WTA-MAX circuit with multichip capability  [Article]

      Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 1998)
      This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA), maximum (MAX), looser-take-all (LTA), and minimum (MIN) circuits. The technique presented is based on current replication ...
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      A Hybrid CMOS-Memristor Neuromorphic Synapse  [Article]

      Azghadi, Mostafa, R.; Linares Barranco, Bernabé; Abbott, Derek; Leong, Philip H.W. (Institute of Electrical and Electronics Engineers, 2017)
      Although data processing technology continues to advance at an astonishing rate, computers with brain-like processing capabilities still elude us. It is envisioned that such computers may be achieved by the fusion of ...
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      A Model for VLSI implementation of CNN image processing chips using current-mode techniques  [Presentation]

      Espejo Meana, Servando Carlos; Rodríguez Vázquez, Ángel Benito; Domínguez Castro, Rafael; Linares Barranco, Bernabé; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1993)
      A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. Current-mode building blocks are presented for the design of CMOS image preprocessing chips (feature ...
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      A modified ART 1 algorithm more suitable for VLSI implementations  [Article]

      Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Elsevier, 1996)
      This paper presents a modification to the original ART 1 algorithm (Carpenter and Grossberg, 1987a, A massively parallel architecture for a self-organizing neural pattern recognition machine, Computer Vision, Graphics, and ...
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      A modular T-mode design approach for analog neural network hardware implementations  [Article]

      Linares Barranco, Bernabé; Sánchez Sinencio, Edgar; Rodríguez Vázquez, Ángel Benito; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1992)
      A modular transconductance-mode (T-mode) design approach is presented for analog hardware implementations of neural networks. This design approach is used to build a modular bidirectional associative memory network. The ...
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      A neuromorphic cortical-layer microchip for spike-based event processing vision systems  [Article]

      Serrano Gotarredona, Rafael; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2006)
      We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format ...
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      A novel CMOS analog neural oscillator cell  [Presentation]

      Linares Barranco, Bernabé; Sánchez Sinencio, Edgar; Newcomb, Robert W.; Rodríguez Vázquez, Ángel Benito; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1989)
      A very flexible programmable CMOS analog neural oscillator cell architecture is presented. The proposed neuron circuit architecture is a hysteretic neural-type pulse oscillator. Its implementation consists of a transconductance ...
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      A precise 90º quadrature OTA-C oscillator tunable in the 50-130-MHz range  [Article]

      Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa; Ramos Martos, J.; Ceballos Cáceres, Joaquín Francisco; Linares Barranco, Alejandro (Institute of Electrical and Electronics Engineers, 2004)
      We present a very-large-scale integration continuous-time sinusoidal operational transconductance amplifiers quadrature oscillator fabricated in a standard double-poly 0.8-μm CMOS process. The oscillator is tunable in the ...