Browsing by Author "Jiménez Garrido, Francisco José"
Now showing items 1-15 of 15
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Article
A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of ...
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Article
A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision
(Institute of Electrical and Electronics Engineers, 2003)A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has ...
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Presentation
A CMOS vision system on-chip with multicore sensory processing ar- chitecture for image analysis above 1,000F/s
(Spie, 2010)This paper describes a Vision-System-on-Chip (VSoC) capable of doing: image acquisition, image processing through on-chip ...
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Presentation
A CNN-driven locally adaptive CMOS image sensor
(Institute of Electrical and Electronics Engineers, 2004)A bioinspired model for mixed-signal array mimics the way in which images are processed in the visual pathway. Focal-plane ...
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Presentation
ACE 16k based stand-alone system for real-time pre-processing tasks
(The International Society for Optical Engineering - SPIE, 2005)This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's ...
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Article
ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs
(Institute of Electrical and Electronics Engineers, 2004)Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible ...
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Presentation
Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
(Institute of Electrical and Electronics Engineers, 2002)A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the ...
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Presentation
CMOS Architectures and circuits for high-speed decision-making from image flows
(The International Society for Optical Engineering (SPIE), 2008)We present architectures, CMOS circuits and CMOS chips to process image flows at very high speed. This is achieved by ...
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Presentation
CMOS realization of a 2-layer CNN universal machine chip
(Institute of Electrical and Electronics Engineers, 2002)Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically ...
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Presentation
Design considerations for a low-noise CMOS image sensor
(SPIE- The International Society for Optical Engineering, 2015)This paper reports a Low-Noise CMOS Image Sensor. Low-noise operation is achieved owing to the combination of a noise-enhanced ...
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PhD Thesis
Diseño CMOS de un sistema de visión “on-chip” para aplicaciones de muy alta velocidad
(2016-02-08)Esta Tesis presenta arquitecturas, circuitos y chips para el diseño de sensores de visión CMOS con procesamiento paralelo ...
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Article
Exploration of spatial-temporal dynamic phenomena in a 32×32-cell stored program two-layer CNN universal machine chip prototype
(World Scientific Publishing, 2003)This paper describes a full-custom mixed-signal chip that embeds digitally programmable analog parallel processing and ...
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Presentation
High-speed global shutter CMOS machine vision sensor with high dynamic range image acquisition and embedded intelligence
(The International Society for Optics and Photonics, 2012)High-speed imagers are required for industrial applications, traffic monitoring, robotics and unmanned vehicles, moviemaking, ...
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Presentation
Programmable retinal dynamics in a CMOS mixed-signal array processor chip
(The International Society for Optical Engineering - SPIE, 2003)The low-level image processing that takes place in the retina is intended to compress the relevant visual information to ...
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Article
Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS
(Institute of Electrical and Electronics Engineers, 2004)Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on ...