Now showing items 1-17 of 17

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      Application of Internode model to global power consumption estimation in SCMOS gates  [Article]

      Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)
      In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its ...
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      Automated performance evaluation of skew-tolerant clocking schemes  [Article]

      Guerrero Martos, David; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Millán Calderón, Alejandro; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Taylor and Francis Online, 2006)
      In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: ...
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      Building a basic membrane computer  [Presentation]

      Millán Calderón, Alejandro; Viejo Cortés, Julián; Quirós Carmona, Juan; Bellido Díaz, Manuel Jesús; Guerrero Martos, David; Ostúa Arangüena, Enrique (Fénix, 2016)
      In this work, we present the building of two well-known membrane com- puters (squares generator and divisor test). Although they are very basic machines they present problems common to every P system (competition, parallel ...
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      Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)  [Article]

      Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David (Springer, 2002-08-27)
      In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model ...
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      Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits  [Chapter of Book]

      Guerrero Martos, David; Wilke, G.; Güntzel, J.L.; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Millán Calderón, Alejandro (Springer, 2003)
      The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on each combinational block of the circuit. A key factor in timing analysis is the election ...
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      Design of a FFT/IFFT module as an IP core suitable for embedded systems  [Presentation]

      Viejo Cortés, Julián; Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Muñoz Blanco, Antonio (IEEE Computer Society, 2007)
      In this work, we have laid the foundations that allow us to accomplish the implementation of a FFT/IFFT module as an IP core. The main objective is to design a configurable optimized core that can be integrated as a ...
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      Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level  [Chapter of Book]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David (Springer, 2002)
      This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic ...
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      Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements  [Presentation]

      Viejo Cortés, Julián; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Ostúa Arangüena, Enrique; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David (IEEE Computer Society, 2006)
      This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network ...
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      Formación de profesores noveles en tecnología electrónica: una primera aproximación  [Presentation]

      Barbancho Concejero, Julio; Guerrero Martos, David; Jiménez Fernández, Carlos Jesús; Valencia Barrero, Manuel (Universidad de Sevilla, Instituto de Ciencias de la Educación, 2005)
      Los profesores universitarios de áreas científicas y técnicas están cada vez más preocupados por desarrollar adecuadamente sus tareas docentes. Una muestra de este hecho se presenta en este trabajo en el que se describe ...
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      Internode: Internal Node Logic Computational Model  [Presentation]

      Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Guerrero Martos, David; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique (IEEE Computer Society, 2003)
      In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal ...
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      Logic-Level Fast Current Simulation for Digital CMOS Circuits  [Chapter of Book]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)
      Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of ...
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      Minimalistic SDHC-SPI hardware reader module for boot loader applications  [Article]

      Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Viejo Cortés, Julián; Guerrero Martos, David (Elsevier, 2017)
      This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having ...
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      NanoFS: a hardware-oriented file system  [Article]

      Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Viejo Cortés, Julián; Guerrero Martos, David (IEEE Computer Society, 2013)
      NanoFS is a novel file system for embedded systems and storage-class memories (like flash) and is specially designed to be directly implemented in hardware. NanoFS is based on an original internal layout intended to achieve ...
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      Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates  [Chapter of Book]

      Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Guerrero Martos, David; Ruiz de Clavijo Vázquez, Paulino; Viejo Cortés, Julián (Springer, 2008)
      Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In ...
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      Signal Sampling Based Transition Modeling for Digital Gates Characterization  [Article]

      Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique (Springer, 2004)
      Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. ...
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      Static Power Consumption in CMOS Gates Using Independent Bodies  [Chapter of Book]

      Guerrero Martos, David; Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2007)
      It has been reported that the use of independent body terminals for series transistors in static bulk-CMOS gates improves their timing and dynamic power characteristics. In this paper, the static power consumption of ...
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