Now showing items 1-20 of 134

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      1D Cellular Automata for Pulse Width Modulated Compressive Sampling CMOS Image Sensors  [Presentation]

      Trevisi, Marco; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2018)
      Compressive sensing (CS) is an alternative to the Shannon limit when the signal to be acquired is known to be sparse or compressible in some domain. Since compressed samples are non-hierarchical packages of information, ...
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      3-Layer CNN Chip for Focal-Plane Complex Dynamics with Adaptive Image Capture  [Presentation]

      Domínguez Matas, Carlos; Carmona Galán, Ricardo; Sánchez Fernández, Francisco J.; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2006)
      This paper presents a CMOS implementation of a layered CNN concurrent with 32times32 photosensors with locally programmable integration time for adaptive image capture. The network is arranged in two layers containing ...
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      3D multi-layer vision architecture for surveillance and reconnaissance applications  [Presentation]

      Földesy, Péter; Carmona Galán, Ricardo; Zarandy, A.; Rekeczky, Csaba; Rodríguez Vázquez, Ángel Benito; Roska, Tamás (Institute of Electrical and Electronics Engineers, 2009)
      The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is ...
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      A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing  [Presentation]

      Carmona Galán, Ricardo; Espejo Meana, Servando Carlos; Domínguez Castro, Rafael; Rodríguez Vázquez, Ángel Benito; Roska, Tamás; Kozek, Tibor; Chua, Leon O. (Institute of Electrical and Electronics Engineers, 1998)
      An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips are available for the CNN Chipset architecture. Time-multiplexed analog routines in the CNN processor ...
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      A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage  [Article]

      Domínguez Castro, Rafael; Espejo Meana, Servando Carlos; Rodríguez Vázquez, Ángel Benito; Carmona Galán, Ricardo; Földesy, Péter; Zarándy, Ákos; Szolgay, Péter; Szirányi, Tamás; Roska, Tamás (Institute of Electrical and Electronics Engineers, 1997)
      This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose ...
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      A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O  [Article]

      Liñán Cembrano, Gustavo; Rodríguez Vázquez, Ángel Benito; Carmona Galán, Ricardo; Jiménez Garrido, Francisco José; Espejo Meana, Servando Carlos; Domínguez Castro, Rafael (Institute of Electrical and Electronics Engineers, 2004)
      This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple ...
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      A 26.5 nJ/px 2.64 Mpx/s CMOS Vision Sensor for Gaussian Pyramid Extraction  [Presentation]

      Suárez, Manuel; Fernández Berni, Jorge; Carmona Galán, Ricardo; Cabello, D.; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2014)
      This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26.5 nJ/px at 2.64 Mpx/s, thus outperforming conventional solutions employing an imager and a separate digital processor. ...
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      A 3-D Chip Architecture for Optical Sensing and Concurrent Processing  [Article]

      Rodríguez Vázquez, Ángel Benito; Carmona Galán, Ricardo; Domínguez Matas, Carlos; Suárez Cambre, Manuel; Brea Sánchez, Víctor Manuel; Pozas, Francisco; Liñán Cembrano, Gustavo; Foldessy, Peter; Zarandy, Akos; Rekeczky, Csaba (SPIE, 2010)
      This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture employs the multi-functional pixel concept to achieve full parallel processing of the information ...
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      A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision  [Article]

      Carmona Galán, Ricardo; Jiménez Garrido, Francisco José; Domínguez Castro, Rafael; Espejo Meana, Servando Carlos; Roska, Tamás; Rekeczky, Csaba; Petrás, István; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2003)
      A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics ...
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      A Bio-Inspired Vision Sensor With Dual Operation and Readout Modes  [Article]

      Leñero Bardallo, Juan Antonio; Hafliger, Philipp Dominik; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2016)
      This paper presents a novel event-based vision sensor with two operation modes: intensity mode and spatial contrast detection. They can be combined with two different readout approaches: pulse density modulation and ...
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      A CMOS 0.18μm 64×64 single photon image sensor with in-pixel 11b time-to-digital converter  [Presentation]

      Vornicu, Ion; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2014)
      The design and characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. It is targeted for time-resolved imaging, in particular 3D imaging. ...
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      A CMOS 8×8 SPAD array for Time-of-Flight measurement and light-spot statistics  [Presentation]

      Vornicu, Ion; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2013)
      The design and simulation of a CMOS 8 × 8 single photon avalanche diode (SPAD) array is presented. The chip has been fabricated in a 0.18μm standard CMOS technology and implements a double functionality: measuring the ...
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      A CMOS Digital SiPM With Focal-Plane Light-Spot Statistics for DOI Computation  [Article]

      Vornicu, Ion; Bandi, Franco; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2017)
      Silicon photomultipliers can be used to infer the depth-of-interaction (DOI) in scintillator crystals. DOI can help to improve the quality of the positron emission tomography images affected by the parallax error. This ...
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      A CMOS Imager for Time-of-Flight and Photon Counting Based on Single Photon Avalanche Diodes and In-Pixel Time-to-Digital Converters  [Article]

      Vornicu, Ion; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito (Editura Academiei Române, 2014)
      The design of a CMOS image sensor based on single-photon avalanche-diode (SPAD) array with in-pixel time-to-digital converter (TDC) is presented. The architecture of the imager is thoroughly described with emphasis on the ...
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      A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors  [Presentation]

      Suárez Cambre, Manuel; Brea Sánchez, Víctor Manuel; Pardo, F.; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2012)
      This paper introduces a two-tier CMOS-3D architecture for generation of Gaussian pyramids, detection of extrema, and calculation of spatial derivatives in an image. Such tasks are included in modern feature detectors, which ...
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      A CNN-driven locally adaptive CMOS image sensor  [Presentation]

      Carmona Galán, Ricardo; Domínguez Matas, Carlos; Cuadri, J.; Jiménez Garrido, Francisco José; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2004)
      A bioinspired model for mixed-signal array mimics the way in which images are processed in the visual pathway. Focal-plane processing of images permits local adaptation of photoreceptor structures in silicon. Beyond simple ...
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      A countinuous-time cellular neural network chip for direction-selectable connected component detection with optical image acquisition  [Presentation]

      Espejo Meana, Servando Carlos; Domínguez Castro, Rafael; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 1994)
      This paper presents a continuous-time Cellular Neural Network (CNN) chip [1] for the application of Connected Component Detection (CCDet) [2]. Projection direction can be selected among four different possibilities. Every ...
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      A Focal-Plane Image Processor for Low Power Adaptive Capture and Analysis of the Visual Stimulus  [Presentation]

      Domínguez Matas, Carlos; Carmona Galán, Ricardo; Sánchez Fernández, Francisco J.; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2007)
      Portable applications of artificial vision are limited by the fact that conventional processing schemes fail to meet the specifications under a tight power budget. A bio-inspired approach, based in the goal-directed ...
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      A high dynamic range image sensor with linear response based on asynchronous event detection  [Presentation]

      Leñero Bardallo, Juan Antonio; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2015)
      This paper investigates the potential of an image sensor that combines event-based asynchronous outputs with conventional integration of photocurrents. Pixels voltages can be read out following a traditional approach with ...
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      A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors  [Presentation]

      Domínguez Castro, Rafael; Espejo Meana, Servando Carlos; Rodríguez Vázquez, Ángel Benito; Carmona Galán, Ricardo (Institute of Electrical and Electronics Engineers, 1997)
      This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially ...