Now showing items 1-20 of 35

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      A 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communications  [Presentation]

      Villegas Calvo, José Alberto; Fiorelli Martegani, Rafaella Bianca; Ginés Arteaga, Antonio José; Doldan Lorenzo, Ricardo; Jalón, Maria Ángeles; Acosta Jiménez, Antonio José; Peralías Macías, Eduardo; Vázquez García de la Vega, Diego (2008)
      This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The ...
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      A 32, x, 32 pixel convolution processor chip for address event vision sensors with 155 ns event latency and 20 meps throughput  [Article]

      Camuñas Mesa, Luis Alejandro; Acosta Jiménez, Antonio José; Zamarreño Ramos, Carlos; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2010)
      This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional frame-constraint vision systems, in event-driven vision there is no need for frames. In frame-free ...
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      A mixed-signal integrated circuit for FM-DCSK modulation  [Article]

      Delgado Restituto, Manuel; Acosta Jiménez, Antonio José; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2005)
      This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental ...
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      A neuromorphic cortical-layer microchip for spike-based event processing vision systems  [Article]

      Serrano Gotarredona, Rafael; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2006)
      We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format ...
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      AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems  [Presentation]

      Serrano Gotarredona, Rafael; Oster, M.; Lichtsteiner, P.; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Kolle Riis, H.; Delbrück, Tobi; Liu, Shih-Chii; Zahnd, S.; Whatley, A.M.; Douglas, R.; Häfliger, P.; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Neural Information Processing Systems Foundation, 2005)
      A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-eventrepresentation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a ...
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      An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors  [Article]

      Camuñas Mesa, Luis Alejandro; Zamarreño Ramos, Carlos; Linares Barranco, Alejandro; Acosta Jiménez, Antonio José; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2012)
      Event-Driven vision sensing is a new way of sensing visual reality in a frame-free manner. This is, the vision sensor (camera) is not capturing a sequence of still frames, as in conventional video and computer vision ...
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      Una aportación al diseño de circuitos integrados CMOS autotemporizados  [PhD Thesis]

      Jiménez Naharro, Raúl (2000-07-10)
      El auge que muestra el campo de los circuitos asíncronos en los últimos años es notorio. Por un lado cada vez se está dedicando más atención en los foros internacionales, con la celebración de congresos específicos (series ...
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      Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores  [Presentation]

      Acosta Jiménez, Antonio José; Bellido Díaz, Manuel Jesús; Barriga Barros, Ángel; Valencia Barrero, Manuel (Universidad de Málaga, 1993)
      La realización de sistemas digitales mediante técnicas autotemporizadas constituye la mejor alternativa para resolver la problemática de las técnicas síncro­nas en circuitos VLSI. En esta comunicación se presenta una mejora ...
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      ASIC-in-the-loop methodology for verification of piecewise affine controllers  [Presentation]

      Martínez Rodríguez, Macarena Cristina; Brox Jiménez, Piedad; Castro, Javier; Tena Sánchez, Erica; Acosta Jiménez, Antonio José; Baturone Castillo, María Iluminada (Institute of Electrical and Electronics Engineers, 2012)
      This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. ...
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      Asymmetric clock driver for improved power and noise performances  [Presentation]

      Castro, Javier; Parra Fernández, María del Pilar; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José (IEEE Computer Society, 2007)
      One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an ...
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      CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking  [Article]

      Serrano Gotarredona, Rafael; Oster, Matthias; Lichtsteiner, Patrick; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Camuñas Mesa, Luis Alejandro; Berner, Raphael; Rivas Pérez, Manuel; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2009)
      This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event ...
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      Circuitos integrados CMOS autotemporizados  [PhD Thesis]

      Acosta Jiménez, Antonio José (1994)
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      Degradation Delay Model Extension to CMOS Gates  [Chapter of Book]

      Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (Springer, 2000)
      This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are ...
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      Determinación del coeficiente de resolución en biestables RS CMOS  [Presentation]

      Bellido Díaz, Manuel Jesús; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José; Barriga Barros, Ángel (Universidad Politécnica de Madrid. Laboratorio de Sistemas Integrados, 1992)
      El diseño de biestables con riesgo de metaestabili­dad requiere que posean coeficientes de resolución adecuados. En este trabajo, se introducen dos métodos para su medida y se comparan con otro previamente reportado. Uno ...
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      Diseño y caracterización de criptocircuitos seguros y resistentes a ataques físicos.  [PhD Thesis]

      Tena Sánchez, Erica (2019-03-11)
      A diario personas de todo el mundo hacen uso de dispositivos electrónicos en los que almacenan o con los que intercambian información privada. La confidencialidad y privacidad es un derecho frente a posibles intrusos, por ...
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      Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits  [Article]

      Acosta Jiménez, Antonio José; Mora Gutiérrez, José Miguel; Castro, Javier; Parra Fernández, María del Pilar (Society of Photo-optical Instrumentation Engineers, 2007)
      The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits and systems. The driver or repeater used to this purpose has effect on the timing characteristics on the ...
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      Gate-Level Simulation of CMOS Circuits Using the IDDM Model  [Presentation]

      Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2001)
      Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is ...
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      HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model  [Presentation]

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (IEEE Computer Society, 2001)
      This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm ...
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      High-speed image processing with AER-based components  [Presentation]

      Serrano Gotarredona, Rafael; Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Jiménez Moreno, Gabriel; Civit Balcells, Antón (IEEE Computer Society, 2006)
      A high speed sample image processing application using AER-based components is presented. The setup objective is to distinguish between two propellers of different shape rotating at high speed (around 1000 revolutions/sec) ...