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Browsing by Author "Acosta Jiménez, Antonio José"
Now showing items 1-20 of 54
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Presentation
A 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communications
Villegas Calvo, José Alberto; Fiorelli Martegani, Rafaella Bianca; Ginés Arteaga, Antonio José; Doldan Lorenzo, Ricardo; Jalón, Maria Ángeles; Acosta Jiménez, Antonio José; Peralías Macías, Eduardo; Vázquez García de la Vega, Diego (2008)This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and ...
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Article
A 32 x 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput
Camuñas Mesa, Luis Alejandro; Acosta Jiménez, Antonio José; Zamarreño Ramos, Carlos; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2011)This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional ...
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Article
A mixed-signal integrated circuit for FM-DCSK modulation
Delgado Restituto, Manuel; Acosta Jiménez, Antonio José; Rodríguez Vázquez, Ángel Benito (Institute of Electrical and Electronics Engineers, 2005)This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential ...
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Article
A neuromorphic cortical-layer microchip for spike-based event processing vision systems
Serrano Gotarredona, Rafael; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2006)We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing ...
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Presentation
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
Serrano Gotarredona, Rafael; Oster, M.; Lichtsteiner, P.; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Kolle Riis, H.; Delbrück, Tobi; Liu, Shih-Chii; Zahnd, S.; Whatley, A.M.; Douglas, R.; Häfliger, P.; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Neural Information Processing Systems Foundation, 2005)A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the ...
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Article
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors
Camuñas Mesa, Luis Alejandro; Zamarreño Ramos, Carlos; Linares Barranco, Alejandro; Acosta Jiménez, Antonio José; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2012)Event-Driven vision sensing is a new way of sensing visual reality in a frame-free manner. This is, the vision sensor (camera) ...
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Master's Final Project
Análisis de técnicas de routing diferencial en CriptoASICs: Adecuación del proceso previo de Place & Route
Guijarro Córdoba, Adrián (2020) -
Presentation
Aplicación del VHDL en prácticas de diseño de sistemas digitales
Acosta Jiménez, Antonio José; Bellido Díaz, Manuel Jesús; Valencia Barrero, Manuel; Barriga Barros, Ángel (Universidad Politécnica de Madrid, 1994) -
PhD Thesis
Una aportación al diseño de circuitos integrados CMOS autotemporizados
Jiménez Naharro, Raúl (2000-07-10)El auge que muestra el campo de los circuitos asíncronos en los últimos años es notorio. Por un lado cada vez se está ...
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Presentation
Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores
Acosta Jiménez, Antonio José; Bellido Díaz, Manuel Jesús; Barriga Barros, Ángel; Valencia Barrero, Manuel (Universidad de Málaga, 1993)La realización de sistemas digitales mediante técnicas autotemporizadas constituye la mejor alternativa para resolver la ...
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Presentation
ASIC-in-the-loop methodology for verification of piecewise affine controllers
Martínez Rodríguez, Macarena Cristina; Brox Jiménez, Piedad; Castro, Javier; Tena Sánchez, Erica; Acosta Jiménez, Antonio José; Baturone Castillo, María Iluminada (Institute of Electrical and Electronics Engineers, 2012)This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable ...
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Presentation
Asymmetric clock driver for improved power and noise performances
Castro, Javier; Parra Fernández, María del Pilar; Valencia Barrero, Manuel; Acosta Jiménez, Antonio José (IEEE Computer Society, 2007)One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation ...
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Presentation
Automated experimental setup for EM cartography to enhance EM attacks
Tena Sánchez, Erica; Casado Galán, Alejandro; Zúñiga González, Virginia; Potestad Ordóñez, Francisco Eugenio; Acosta Jiménez, Antonio José (2022)Side-channel attacks are a real threat, exploiting and revealing the secret data stored in our electronic devices ...
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Article
CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking
Serrano Gotarredona, Rafael; Oster, Matthias; Lichtsteiner, Patrick; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Camuñas Mesa, Luis Alejandro; Berner, Raphael; Rivas Pérez, Manuel; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2009)This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating ...
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Final Degree Project
Cifrado y descifrado de imágenes con Matlab para almacenamiento seguro
Espejo Vázquez, José María (2020) -
PhD Thesis
Circuitos integrados CMOS autotemporizados
Acosta Jiménez, Antonio José (1994) -
Presentation
Concepción de un microprocesador: de la especificación a la realización
Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José (Universidad Politécnica de Madrid, 2000) -
Chapter of Book
Degradation Delay Model Extension to CMOS Gates
Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (Springer, 2000)This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic ...
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Presentation
Delay degradation effect in submicronic CMOS inverters
Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Acosta Jiménez, Antonio José; Barriga Barros, Ángel; Valencia Barrero, Manuel (Université Catholique de Louvain, 1997)This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS ...
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Final Degree Project
Desarrollo de setup experimental y control automático de instrumentos para optimizar ataques de canal lateral
Casado Galán, Alejandro (2022)Un ataque de canal lateral explota un observable físico proveniente de un dispositivo criptográfico con el fin de extraer ...