Ponencia
Modeling of Real Bistables in VHDL
Autor/es | Acosta Jiménez, Antonio José
Barriga Barros, Ángel Valencia Barrero, Manuel Bellido Díaz, Manuel Jesús Huertas Díaz, José Luis |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 1993 |
Fecha de depósito | 2017-01-18 |
Publicado en |
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ISBN/ISSN | 0-8186-4350-1 |
Resumen | A complete VHDL model of bistables including their
metastable operation is presented. An RS-NAND latch
has been modelled as a basic structure, orienting its
implementation towards its inclusion in a cell library.
Two ... A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two applications are included: description of a more complex latch (D-type) and description of a circuit containing three latches where metastable signals are propagated. Simulation results show that the presented niodel provides very realistic information about the device behavior, which until now had to be obtained through electric simulation. |
Cita | Acosta Jiménez, A.J., Barriga Barros, Á., Valencia Barrero, M., Bellido Díaz, M.J. y Huertas, J.L. (1993). Modeling of Real Bistables in VHDL. En Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference (460-465), Hamburg, Germany: IEEE Computer Society. |
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Modeling of real.pdf | 551.0Kb | [PDF] | Ver/ | |