• Artículo
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      Application of Internode model to global power consumption estimation in SCMOS gates 

      Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)
      In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based ...
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      Logic-Level Fast Current Simulation for Digital CMOS Circuits 

      Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)
      Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to ...
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      Network Time Synchronization: A Full Hardware Approach 

      Juan Chico, Jorge; Viejo Cortés, Julián; Bellido Díaz, Manuel Jesús (Springer, 2012)
      Complex digital systems are typically built on top of several abstraction levels: digital, RTL, computer, operating system ...
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      Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates 

      Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Guerrero Martos, David; Ruiz de Clavijo Vázquez, Paulino; Viejo Cortés, Julián (Springer, 2008)
      Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of ...
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      Static Power Consumption in CMOS Gates Using Independent Bodies 

      Guerrero Martos, David; Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2007)
      It has been reported that the use of independent body terminals for series transistors in static bulk-CMOS gates improves ...